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www.irf.com 1 IP2002 features: ? output current 30a continuous with no derating up to t pcb = 90c and t case = 90c ? operating frequency up to 1mhz ? dual sided heatsink capable ? very small 11mm x 11mm x 2.6mm profile ? ip2001 footprint compatible ? internal features minimize layout sensitivity * ? optimized for very low power losses synchronous buck multiphase optimized bga power block integrated power semiconductors, drivers & passives description the IP2002 is a fully optimized solution for high current synchronous buck multiphase applications. board space and design time are greatly reduced because most of the components required for each phase of a typical discrete-based multiphase circuit are integrated into a single 11mm x 11mm x 2.6mm bga power block. the only additional components required for a complete multiphase converter are a pwm ic, the external inductors, and the input and output capacitors. ipowir technology offers designers an innovative board space saving solution for applications requiring high power densities. ipowir technology eases design for applications where component integration offers benefits in performance and functionality. ipowir technology solutions are also optimized internally for layout, heat transfer and component selection. IP2002 power block 03/20/03 pd - 94568a * all of the difficult pcb layout and bypassing issues have been addressed with the internal design of the ipowir block. there are no concerns about double pulsing, unwanted shutdown, or other malfunctions which often occur in switching power supplies. the ipowir block will function normally without any additional input power supply bypass capacitors. however, for reliable long term operation it is recommended that at least fou r 10uf ceramic input decoupling capacitors are provided to the v in pin of each power block. no additional bypassing is required on the v dd pin. IP2002 internal block diagram mosfet driver with dead time cont rol v in v sw pgnd prdy enable pwm v dd sgnd mosfet driver with dead time cont rol v in v sw pgnd prdy enable pwm v dd sgnd
www.irf.com 2 IP2002 all specifications @ 25c (unless otherwise specified) c measurement were made using four 10uf (tdk c3225x7r1c106m or equiv.) capacitors across the input (see fig. 8). d not associated with the rise and fall times. does not affect power loss (see fig. 9). parameter symbol min typ max units conditions supply voltage v dd 4.6 5.0 5.5 v input voltage range v in 3.0 - 13.2 v see figs. 2 & 3 output voltage range v out 0.9 - 3.3 v see figs. 2, 4 & 8 output current range i out --30 a see fig. 2 operating frequency fsw 150 - 1000 khz see figs. 2 & 5 operating duty cycle d - - 85 % recommended operating conditions : absolute maximum ratings : electrical specifications @ v dd = 5v (unless otherwise specified) : parameter symbol min typ max units conditions block power loss c p blk - 7.2 8.9 w v in = 12v, v out = 1.3v, turn on delay d t d(on) -63- i out = 30a, f sw = 1mhz turn off delay d t d(off) -26- v in quiescent current i q-vin - - 1.0 ma enable = 0v, v in = 12v v dd quiescent current i q-vdd --10 a enable = 0v, v dd = 5v under-voltage lockout uvlo start threshold v start 4.2 4.4 4.5 v hysteresis v hys-uvlo - .05 - enable enable input voltage high v ih 2.0 - - v input voltage low v il - - 0.8 power ready prdy logic level high v oh 4.5 4.6 - v v dd = 4.6v, i load = 10ma logic level low v ol - 0.1 0.2 v dd < uvlo threshold, i load = 1ma pwm input pwm logic level high v oh 2.0 - - v logic level low v ol - - 0.8 ns parameter min typ max units conditions v in to pgnd - - 16 v v dd to sgnd - - 6.0 v pwm to sgnd -0.3 - v dd +0.3 v not to exceed 6.0v enable to sgnd -0.3 - v dd +0.3 v not to exceed 6.0v output rms current - - 30 a block temperature -40 - 125 c
www.irf.com 3 IP2002 pin description table pin name ball designator pin function v dd a1 ? a3, b1 ? b3 supply voltage for the internal circuitry. v in a5 ? a12, b5 ? b12, c5 - c10 input voltage for the dc-dc converter. pgnd c11, c12, d11, d12, e11, e12, f6, f7, f12, g6, g7, g12, h6, h7, h12, j6, j7, j12, k5 ? k7, k12, l5, l6, l12, m5 ? m7, m12 power ground - connection to the ground of bulk and filter capacitors. v sw d5 ? d10, e5 ? e10, f8 ? f11, g8 ? g11, h8 ? h11, j8 ? j11, k8 ? k11, l8 ? l11, m8 ? m11 switching node - connection to the output inductor. sgnd c1 ? c3, d1 ?d3, e1 ?e3 signal ground. enable f1 when set to logic level high, internal circuitry of the device is enabled. when set to logic level low, the prdy pin is forced low, the control and sychronous switches are turned off, and the supply current is less than 10 a. prdy k1 power ready - this pin indicates the status of enable or v dd . this output will be driven low when enable is logic low or when v dd is less than 4.4v (typ.). when enable is logic high and v dd is greater than 4.4v (typ.), this output is driven high. this output has a 10ma source and 1ma sink capability. pwm h1 ttl-level input signal to mosfet drivers. nc b4, c4, d4, e4, f2 ? f4, g2 ? g4, h2 ? h4, j1, j2 ? j4, k3, l1, l2, m1 ? m4 this pin is not for electrical connection. it should be attached only to dead copper.
www.irf.com 4 IP2002 fig. 1: power loss vs. current fig. 2: safe operating area (soa) vs. t pcb & t case 0 1 2 3 4 5 6 7 8 9 10 11 0 5 10 15 20 25 30 output current (a) power loss (w) v in = 12v v out = 1.3v f sw = 1mhz t blk = 125c l = 0.30uh maximum typical 0 102030405060708090100110120 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 0 102030405060708090100110120 pcb temperature (oc) output current (a) safe operating area v in = 12v v out = 1.3v f sw = 1mhz l = 0.30uh case temperature ( oc) t x
www.irf.com 5 IP2002 fig. 7: i dd vs. frequency fig. 5: normalized power loss vs. frequency fig. 3: normalized power loss vs. v in fig. 4: normalized power loss vs. v out typical performance curves fig. 6: normalized power loss vs. inductance 0.70 0.75 0.80 0.85 0.90 0.95 1.00 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 switching frequency (khz) power loss (normalized) -10.5 -8.5 -6.5 -4.5 -2.5 -0.5 soa temp adjustment (oc) v in = 12v v out = 1.3v i out = 30a l = 0.30uh t blk = 125c 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 345678910111213 input voltage (v) power loss (normalized) -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 soa temp adjustment (oc) v out = 1.3v i out = 30a f sw = 1mhz l = 0.30uh t blk = 125c 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 0.81.21.62.02.42.83.23.6 output voltage (v) power loss (normalized) -3.5 -1.5 0.5 2.5 4.5 6.5 8.5 10.5 soa temp adjustment (oc) v in = 12v i out = 30a f sw = 1mhz l = 0.30uh t blk = 125c 0 10 20 30 40 50 60 70 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 switching frequency (khz) average i dd (ma) does not include prdy current t blk = 25c 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output inductance (uh) power loss (normalized) -1.1 -0.6 -0.1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 soa temp adjustment (oc) v in = 12v v out = 1.3v i out = 30a f sw = 1mhz t blk = 125c
www.irf.com 6 IP2002 adjusting the power loss and soa curves for different operating conditions to make adjustments to the power loss curves in fig. 1, multiply the normalized value obtained from the curves in figs. 3, 4, 5 or 6 by the value indicated on the power loss curve in fig. 1. if multiple adjustments are required, multiply all of the normalized values together, then multiply that product by the value indicated on the power loss curve in fig. 1. the resulting product is the final power loss based on all factors. see example no. 1. to make adjustments to the soa curve in fig. 2, determine your maximum pcb temp & case temp at the maximum operating current of each IP2002. then, add the correction temperature from the normalized curves in figs. 3, 4, 5 or 6 to the t x axis intercept (see procedure no. 2 above) in fig. 2. when multiple adjustments are required, add all of the temperatures together, then add the sum to the t x axis intercept in fig. 2. see example no. 2. operating conditions for the following examples: output current = 30a input v olt age = 10v inductor = 0.2uh output v olt age = 3.3v sw freq= 900khz example 1) adjusting for maximum power loss: (fig. 1) maximum power loss = 11w (fig. 3) normalized power loss for input voltage 0.98 (fig. 4) normalized power loss for output voltage 1.24 (fig. 5) normalized power loss for frequency 0.95 (fig. 6) normalized power loss for inductor value 1.02 adjusted power loss = 11w x 0.98 x 1.24 x 0.95 x 1.02 12.95w applying the safe operating area (soa) curve the soa graph incorporates power loss and thermal resistance information in a way that allows one to solve for maximum current capability in a simplified graphical manner. it incorporates the ability to solve thermal problems where heat is draw n out through the printed circuit board and the top of the case. procedure 1) draw a line from case temp axis at t case to the pcb temp axis at t pcb . 2) draw a vertical line from the t x axis intercept to the soa curve. 3) draw a horizontal line from the intersection of the vertical line with the soa curve to the y axis. the point at which the horizontal line meets the y-axis is the soa current. 0 102030405060708090100110120 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 0 102030405060708090100110120 pcb temperature (oc) output current (a) safe operating area v in = 12v v out = 1.3v f sw = 1mhz l = 0.30uh case temperature ( oc) t x 1 2 3
www.irf.com 7 IP2002 v sw p gnd prdy enable v dd s gnd a a dc v average input voltage average input current average output current averaging circuit v average output voltage dc v average vdd voltage a average vdd current ip2001 p in = v in average x i in average p dd = v dd average x i dd average p out = v out average x i out average p loss = (p in + p dd ) - p out v in pwm t d(on) t d(off) pwm v sw 90% 10% 90% 10% fig 8. power loss test circuit fig 9. timing diagram IP2002 average output voltage (v out ) example 2) adjusting for soa temperature: (fig. 3) normalized soa temperature for input voltage -0.6c (fig. 4) normalized soa temperature for output voltage 8.4c (fig. 5) normalized soa temperature for frequency -1.8c (fig. 6) normalized soa temperature for inductor value 1.1c t x axis intercept temp adjustment = - 0.6c + 8.4c - 1.8c + 1.1c 7.1c assuming t case = 100c & t pcb = 90c: the following example shows how the soa current is adjusted for a t x increase of 7.1c. 0 102030405060708090100110120 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 0 102030405060708090100110120 pcb temperature (oc) output current (a) safe operating area v in = 12v v out = 1.3v f sw = 1mhz l = 0.30uh case temperature ( oc) t x unadjusted soa current adjusted soa current
www.irf.com 8 IP2002 4-phase reference design schematic title number revision size r6 200 c1 6800pf r1 3.92k r2 3.92k r3 4.42k r4 20k c2 10uf vdd1 sgnd1 pwm1 enable1 prdy1 vin1 vsw1 pgnd1 IP2002-1 c15 100uf c16 100uf l1 0.3uh l2 0.3uh r5 2.49k r7 2.49k +5v c3 10uf c4 10uf c6 10uf c7 10uf enable1 vsw1 vsw2 c5 10uf c8 10uf tp6 vsw1 tp7 vsw2 l3 0.3uh c9 10uf c10 10uf vsw3 c11 10uf tp8 vsw3 l4 0.3uh c12 10uf c13 10uf vsw4 c14 10uf tp9 vsw4 r9 2.49k r8 2.49k vout vin vin vin vin r10 0 r12 0 r13 0 r11 0 tp14 pgnd tp15 pgnd tp16 pgnd tp5 pgood tp12 vout tp11 vout tp10 vout tp18 vin tp21 vouts tp22 pgnds vouts r16 10k r17 10k r18 10k c33 10uf c30 10uf c32 10uf c31 10uf r19 10k vouts pgnds vsen 6 comp 3 pwm4 16 pgood 2 isen4 15 vcc 1 isen1 14 droop 4 pwm1 13 fb 5 pwm2 12 fs/en 7 isen2 11 gnd 8 isen3 10 pwm3 9 u1 isl6558cb c17 100uf c18 100uf c19 100uf c20 100uf c21 100uf c22 100uf r21 10k r22 open +5v vdd2 sgnd2 pwm2 enable2 prdy2 vin2 vsw2 pgnd2 IP2002-2 +5v enable2 r23 10k r24 open +5v vdd3 sgnd3 pwm3 enable3 prdy3 vin3 vsw3 pgnd3 IP2002-3 +5v enable3 r25 10k r26 open +5v vdd4 sgnd4 pwm4 enable4 prdy4 vin4 vsw4 pgnd4 IP2002-4 +5v enable4 r27 10k r28 open +5v r29 open r30 open +5v +5v +5v c25 8.2pf c26 1800pf vin vdd 12v / 5v converter vin +5v IP2002_4 phase demo board c34 0.1uf r31 3.92k r32 4.42k prdy1 prdy2 prdy3 prdy4 c37 0.22uf 2 3 1 d1 cmpd3003a prdy3 c38 0.22uf prdy4 c35 0.22uf prdy1 c36 0.22uf prdy2 c41 330uf c40 330uf c39 330uf tp19 pgnd 2 3 1 d2 cmpd3003a tp13 vins tp17 pgnds c42 open c43 open c44 open c45 open c46 10uf c47 open r36 open r35 0 c27 1uf c29 10uf u6
www.irf.com 9 IP2002 refer to the following application notes for detailed guidelines and suggestions when implementing ipowir technology products: an-1028: recommended design, integration and rework guidelines for international rectifier?s ipowir technology bga packages this paper discusses the assembly considerations that need to be taken when mounting ipowir bga?s on printed circuit boards. this includes soldering, pick and place, reflow, inspection, cleaning and reworking recommendations. an-1029: optimizing a pcb layout for an ipowir technology design this paper describes how to optimize the pcb layout design for both thermal and electrical performance. this includes placement, routing, and via interconnect suggestions. an-1030: applying ipowir products in your thermal environment this paper explains how to use the power loss and soa curves in the data sheet to validate if the operating conditions and thermal environment are within the safe operating area of the ipowir product. an-1047: graphical solution for two branch heatsinking safe operating area detailed explanation of the dual axis soa graph and how it is derived. 4-phase reference design bill of materials quantity designator v alue 1 v alue 2 type 2 tolerance package mfr. mfr. part no. 1 c1 6800pf 50v x7r 10% 0805 phicomp 08052r682k9bb0 17 c10 c11 c12 c13 c14 c3 c30 c31 c32 c33 c4 c46 c5 c6 c7 c8 c9 10.0uf 16v x5r 10% 1206 murata grm31cr61c106kc31b 8 c15 c16 c17 c18 c19 c20 c21 c22 100uf 6.3v x5r 20% 1210 tdk c3225x5r0j107m 2 c2 c29 10.0uf 6.3v x5r 10% 1206 tdk c3216x5r0j106k 1 c25 8.20pf 50v npo 3% 0805 phicomp 0805cg829c9bb0 1 c26 1800pf 50v x7r 10% 0805 phicomp 08052r182k9bb0 1 c27 1.00uf 16v x7r 10% 0805 murata grm40x7r105k016 1 c28 0.010uf 50v x7r 10% 0805 tdk c2012x7r1h103kt 1 c34 0.100uf 50v x7r 10% 0805 rohm mch215c104kp 4 c35 c36 c37 c38 0.22uf 6.3v x5r 10% 0603 tdk c1608x5r0j224k 3 c39 c40 c41 330uf 16v wa series 20% smd panasonic eef-wa1c331p 5 c42 c43 c44 c45 c47 open - - - - - - 3 r1 r2 r31 3.92k 1/8w thin film 0.10% 0805 bc component 2312-241-73922 5 r10 r11 r12 r13 r35 0 1/8w thick film <50m 0805 rohm mcr10ezhj000 9 r16 r17 r18 r19 r21 r23 r25 r27 r34 10.0k 1/8w thick film 1% 0805 koa rk73h2a1002f 2 r3 r32 4.42k 1/8w thin film 0.10% 0805 bc component 2312-241-74422 1 r33 30.1k 1/8w thick film 1% 0805 koa rk73h2a3012f 1 r4 20.0k 1/8w thick film 1% 0805 koa rk73h2a2002f 4 r5 r7 r8 r9 2.49k 1/8w thick film 1% 0805 koa rk73h2a2491f 1 r6 200 1/8w thick film 1% 0805 koa rk73h2a2000f 7 r22 r24 r26 r28 r29 r30 r36 open - - - - - - 2 d1 d2 30v 200ma schottky - sot23 central cmpd3003a 1 d5 40v 2.1a schottky - d-64 irf 10mq040n 1 d6 30v 100ma schottky - sot23 central cmpsh-3 4 l1 l2 l3 l4 0.3uh 36a ferrite 20% smt panasonic etqp2h0r3bfa 1 l5 15uh 0.70a ferrite 20% smt coilcraft 1008ps-153m 1 u1 4.5 - 5.5v 0.8 - 5v pwm controller 0 - 70c 16 ld soic intersil isl6558cb 4 u2 u3 u4 u5 30a - power block - 11mm x 11mm international rect IP2002 1 u6 4.7 - 25v 1.8 - 5v pwm controller -40 to +85c s6 linear technology lt1616
www.irf.com 10 IP2002 recommended pcb footprint (top view) dimensions shown in inches (millimeters) v dd nc v in pgnd enable prdy v sw pwm nc nc nc nc nc nc nc nc nc nc nc nc nc pgnd sgnd
www.irf.com 11 IP2002 mechanical drawing 0.15 [.006] c 0.12 [.005] c 2. dimensions are shown in millimeters [ inches] . 3. controlling dimension: millimeter 1. dimensioning & tolerancing per asme y14.5m-1994. notes: b a 0.15 [.006] c 4x 22x 0.15 [.006] c a b 0.08 [.003] c 133x ? 0.55 [.0216] 0.45 [.0178] 2x 2x top view bottom view side view c package body. ball diameter, in a plane parallel to datum c. spherical crowns of the solder balls. 4. solder ball position designation per jesd 95-1, spp-010. 7 solder ball diameter is measured at the maximum solder 5 primary datum c (seating plane) is defined by the 6 bilateral tolerance zone is applied to each side of the 7 5 6 6 ball a1 corner id 11.00 [.433] 0.40 [.016] 0.80 [.032] 11.00 [.433] 2.76 [.1087] 2.46 [.0969] 2.31 [.0909] 2.11 [.0831] (4x 1.1 [.043]) 0.45 [.0177] 0.35 [.0138]
www.irf.com 12 IP2002 data and specifications subject to change without notice. this product has been designed and qualified for the industrial market. qualification standards can be found on ir?s web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 8/01 tape & reel information part marking IP2002 xxxx 0123 1. outline conforms to eia-481 & eia-541. notes: 16mm feed direction 24mm 0123 601000 IP2002 0123 IP2002 601000

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